What are the circuit design schemes for the RS485 interface in EMC testing?

1. RS485 interface 6KV lightning protection circuit design scheme

Overview of interface circuit design:

RS485 is used for communication between equipment and computer or other equipment. In product application, its multiple lines are mixed with power supply, power signal, etc., which has potential EMC hazards. Based on the principle of EMC testing, this scheme designs relevant interference suppression and anti-sensitivity, and solves the EMC testing problem from the design level.

2. Circuit EMC design description:

(1) Key points of circuit filter design:

L1 is a common-mode inductance, which can suppress the internal and external interference of the board, improve the anti-interference ability of the product, and reduce the external radiation of 429 signal lines. The selection range of common-mode inductance impedance is 120 Ω/100MHz~2200 Ω/100MHz, and the typical value is 1000 Ω/100MHz;

C1.C2 is a filter capacitor that provides a low impedance return path for interference, which can effectively reduce the external common-mode current and filter external interference; The selection range of capacitance value is 22PF~1000pF, and the typical value is 100pF; If the signal line has insulation and voltage resistance requirements to the metal shell, the voltage resistance of the two filter capacitors of the differential line to the ground should be considered;

When there are multiple nodes on the circuit, the filter capacitance value should be reduced or removed. C3 is the bridging capacitance between the interface ground and the digital ground. The typical value is 10000 pF. The C3 capacitance value can be adjusted according to the test situation;

(2) Key points of circuit lightning protection design:

In the EMC test, in order to meet the requirements of IEC61000-4-5 or GB17626.5 standard, common mode 6KV and differential mode 2KV lightning protection test, D IV is the three-level protection circuit formed by the three-terminal gas discharge tube, which can suppress the common mode and differential mode surge interference on the line and prevent the interference from affecting the next level of electrical circuit through the signal line;

The nominal voltage VBRW of gas discharge tube is required to be greater than 13V, and the peak current IPP is required to be greater than or equal to 143A;

The peak power WPP is required to be greater than or equal to 185999W;

PTC1.PTC2 is a secondary protection circuit formed by thermistor, with a typical value of 10 Ω/2W;

In order to ensure the smooth conduction of the gas discharge tube, the resistance must be increased for partial voltage to ensure that most of the energy is eliminated through the gas discharge tube;

D1~D3 are TSS tubes (semiconductor discharge tubes) to form the third-level protection circuit. The nominal voltage VBRW of TSS tubes is required to be greater than 8V, and the peak current IPP is required to be greater than or equal to 143A; The peak power WPP is required to be greater than or equal to 114444W;

3. Interface circuit design note:

If the equipment is a metal shell, the single board can divide the interface ground independently, and the metal shell is directly electrically connected with the interface ground, and the single board ground is connected with the interface ground through a 10000 pF capacitor;

If the equipment is a non-metallic shell, the interface grounding PGND is directly electrically connected with the single board digital grounding GND.

2、 PCB design

1RS485 interface circuit layout

Figure 1 RS485 interface filter and protection circuit layout

Program features:

(1) Protective devices and filter elements shall be placed close to the interface and shall be compact and tidy. According to the rule of protection before filtering, try to avoid line twists and turns;

(2) Common mode inductance and jumper capacitance shall be placed in the isolation belt.

Scheme analysis:

(1) The interface and interface filter protection circuit shall not be wired, and high-speed or sensitive devices shall not be placed;

(2) The projection layer under the isolation belt shall be cleared and wiring is prohibited.

2. RS485 interface circuit separation design

Figure 2. RS485 interface circuit grounding design layout

Program features:

(1) Inhibit the internal board noise transmitting radiation to the outside through the RS485 interface. In order to enhance the board's immunity to external interference, add filter elements at the RS485 interface to suppress the noise. Divide the interface ground with the position of the filter element as the boundary;

(2) The isolation belt can selectively add capacitance as the connection between the two places. The value of capacitance C4.C5 is recommended to be 1000pF. The online series common-mode inductance CM and capacitance wave are connected to the interface ground in parallel with GDT and TVS pipeline protection; All protective devices are placed near the interface, and the common-mode inductance CM is placed in the isolation belt. The specific layout is shown in the figure.

Scheme analysis:

(1) When there is a circuit with poor compatibility or incompatibility between the interface and the board, it is necessary to conduct "ground separation" processing between the interface and the board, that is, processing according to different port voltages. Set the level signal and transmission rate respectively. "Ground separation" can prevent the superposition of incompatible circuit return signals and impedance coupling of common ground wire;

(2) The phenomenon of "ground separation" will lead to an increase in impedance of the return signal when it crosses the isolation band, thus leading to a great risk of EMC testing. Therefore, the return path of the signal is provided between the isolation bands through capacitors.