EMC process design has an important impact on EMI

Various control technologies are usually used for EMC design. In general, the closer to the EMI source, the lower the cost of achieving EM control. PCB integrated circuit chip is EMI. Therefore, if we can deeply understand the internal characteristics of integrated circuit chip, we can simplify the EMI control of its PCB in system-level design. When considering EMI control, design engineers and PCB board-level design engineers choose IC chips. Some characteristics of integrated circuits, such as packaging type, bias voltage and chip: process technology (such as CMoS, ECI) have a great impact on electromagnetic interference. The following will focus on the impact of IC on EMI control.

Source of integrated circuit EMl

The EMI sources of integrated circuits in PCB mainly include: the conversion of digital integrated circuits from high logic to low logic caused by the square wave signal frequency generated at the output end, or the conversion from low logic to high logic EMl signal voltage, signal current electric field and the capacitance and inductance of the magnetic field chip itself.

The square wave generated at the output end of the integrated circuit chip contains a wide range of sinusoidal harmonic components. This is the EMI frequency component that engineers are concerned about. The EMI frequency is also known as the transmission bandwidth of the EMI transmission bandwidth time (not the signal frequency).

The formula for calculating EMI transmission bandwidth is as follows: f=0.35/tr

In the type, the factory is the frequency, and the unit is GHz; 7r is the rising or falling time of the signal, in ns.

From the above formula, we can see that if the switching frequency of the circuit is 50MHz, the rise time of the integrated circuit chip is 1ns, so the maximum EMI transmission frequency of the circuit will reach 350MHz, which is far greater than the switching frequency of the circuit. If the rise time of remittance is 5 ribs, Fs, the maximum EMI RF of the circuit will be as high as 700MHz.

Each voltage value in the circuit corresponds to a certain current, and each current has a corresponding voltage. When each current. IC These signal voltages and currents generate electric and magnetic fields. The highest frequency of these electric and magnetic fields is the transmission bandwidth. The intensity of electric and magnetic fields and the percentage of external radiation are not only functions of the signal rise time, but also depend on the capacitance and inductance control between the signal source and the load point. Therefore, the signal source is located in the sink of the PCB, while the load is located in other ICs. These ICs may or may not be on the PCB. In order to effectively control EMI, we should not only pay attention to exchange; The capacitance and inductance of Barbara itself also need to pay attention to the capacitance and inductance of PCB.

When the tank between the signal voltage and the signal circuit is not tight, the capacitance of the circuit will be reduced, thus weakening the inhibition of the electric field, thus reducing the increase of capacitance EMI; So is the current in the circuit. If the kettle between the current and the return path is not closed; Well, it will inevitably increase the inductance on the circuit, thus enhancing the magnetic field, and eventually lead to EMI addition. This fully shows that poor control of electric field usually leads to poor suppression of magnetic field. The measures to control the electromagnetic field in the circuit board and the measures to suppress the IC electromagnetic field packaging are roughly similar. PCB design, IC packaging design will have a great impact on EMI.

A considerable part of electromagnetic radiation in the circuit is caused by voltage transients in the power bus. When the output level of remittance is: the electromagnetic radiation PCB line connected to the jump and drive is logically "high", the sink chip will absorb the current from the power supply to provide the energy required by the output level every month. As far as the UHF current generated by continuous conversion is concerned, the rolling-off network on the power bus aunt PCB stops the output stage of remittance. If the signal rise time of the output stage is 1.0ns, then the IC should absorb enough current from the power supply to drive the transmission line on the PCB in such a short time of 1.0ns. The transient change of voltage on the power bus depends on the application on the power supply j-line path. Sensing and absorbing current and current transmission time. The transient change of voltage is defined by the formula, L is the inductance value on the current transmission path; Dj represents the change of current in the signal rise time interval; Dz represents the change of D stream transmission time (signal rise time).

Because IC pins and internal circuits are part of the power bus, the time to absorb current and output signal also depends on the remittance technology to a certain extent. Therefore, selecting the appropriate remittance can largely control the three elements mentioned in the above formula.

Packaging features in EMI control

IC packaging usually includes silicon chips, a small internal PCB and pads. The silicon-based chip is installed on the small 64PCB, and the connection between the silicon-based chip and the pad is realized through the binding line. In some packages, it can also be directly connected to the PCB in the small package to realize the connection between the signal on the silicon-based chip and the power supply and the corresponding pins on the assembly package, so as to realize the external extension of the signal and power nodes on the silicon-based chip. Therefore, the transmission path of power supply and signal includes the connection between the filling base chip and the small chip PCB, the PCB connection and the input and output pins of the assembly package. The control of capacitance and home feeling (corresponding to electric field and magnetic field) largely depends on the design of the entire transmission path. Some design characteristics will directly affect the chip packaging of the entire design IC capacitor and inductor.

First, look at the connection mode between the silicon-based chip and the internal small circuit board. Many integrated chips use binding wires to connect the neck silicon chip and the internal small circuit board. This is a very thin 6t wire between the silicon chip and the internal small circuit board. Due to the coefficient of thermal expansion of silicon-based chips and internal small circuit boards, this technology has been widely used (CU). Similar chips themselves are silicon-based devices, and their coefficient of thermal expansion is very different from that of typical similar PCB materials (such as epoxy resin). For example, if the electrical connection point of the silicon-based chip is directly installed on the internal PCB, after a relatively short period of time, the change of the internal temperature of the IC package will lead to thermal expansion and cold contraction, and the connection in this way will fail due to fracture. Binding line is a leader method adapted to this special environment. It can bear bending deformation of large load and is not easy to break

The problem with using binding wire is that the increase of current loop area of each signal or power line will lead to the increase of inductance value. The excellent design to obtain a lower inductance value is to realize the direct connection between the silicon-based chip and the internal PCB, which means that the connection point of the silicon-based chip is directly connected to the PCB pad. This requires the use of a special PCB substrate material, which should have a very low coefficient of thermal expansion. The selection of this material will lead to an increase in the overall cost of remittance chips, so chips using this technology are not common, but as long as ICs directly connected to silicon-based chips and carrier PCBs exist: it is feasible in the design scheme, so IC equipment using this scheme is a better choice.

Generally speaking, in the packaging design, the main consideration in the selection of integrated circuit chips is to reduce the inductance and increase the capacitance between the signal and the corresponding circuit or between the power supply and the ground. For example, small-space surface mounting and large-space surface mounting: Compared with the process, chips packaged by small-space surface mounting process should be preferred. All chips packaged by these two surface mounting processes are better than through-hole lead type packaging. Compared with any commonly used packaging type, BGA packaging chip has the lowest lead inductance. From the perspective of capacitance and inductance control, small packaging and finer spacing usually represent performance improvement.

An important feature of lead structure design is pin distribution. Since the value of inductance and capacitance depends on the proximity between the signal or power supply and the return path, enough return paths should be considered.

The power pin and ground pin shall be distributed in pairs, and each power pin shall have corresponding ground pin adjacent to each other. In this wire structure, multiple power pin and ground pin pairs shall be distributed. These two features will greatly reduce the inductance between the power supply and the ground, help reduce the voltage transient changes on the power bus, and thus reduce the voltage EAdI. Because of habit, many foreign exchange chips on the market do not fully follow the above design rules. However, IC designers and manufacturers have a deep understanding of the advantages of this design method, so it is a new IC design and release chip IC manufacturers pay more attention to power connection.

Ideally, each signal pin needs to be assigned an adjacent signal return pin (such as ground pin). This is not the case in practice. Many IC manufacturers adopt other compromise methods. In BGA packaging, an effective design method is to set a signal return pin in the center of each group of eight signal pins. In this pin arrangement, there is only one pin distance between each signal and the signal return path. Generally speaking, it is unrealistic to place the signal return path in the center of the signal group for the quad flatpack (QFP) or other gull wing (Gullw cut g) package IC. Even so, make sure to place a signal return pin every 4 to 6 pins. It should be noted that different transmission technologies may use different signal return voltages. Some ICs use the ground pin (such as TIL devices) as the return path of the signal, while some ICs use the power pin (such as most) ECI as the return path of the signal, and some device ICs use both the power pin and the ground pin (such as most) CMoS devices) as the return path of the signal. Therefore, the design engineer must be familiar with the design IC chip logic series used in the design and understand its relevant work.

The reasonable distribution of power supply and ground pins in IC chips can not only reduce EMI, but also greatly improve the ground bounce effect. When the device driving the transmission line tries to pull the transmission line down to low logic, the earth bounce reflection still remains above the low logic closed level, and the earth bounce reflection may cause circuit failure or failure.

Another important issue for IC to pay attention to is the design of the internal PCB of the chip. The internal PCB is usually the largest component of the IC package. If the capacitance and inductance of the internal PCB are strictly controlled, the overall EMI performance of the system will be greatly improved. If it is two floors. At least one side of the PCB board is required to be a continuous plane layer, and the other side of the PCB board is the wiring layer of power supply and signal. It is more ideal to have four layers of PCB. The middle two layers are power supply and ground layer, and the outer two layers are signal wiring layer. Because the internal PCB inside the packaging is usually very thin, the design of the four-layer board structure will lead to two wiring layers with high capacitance and low inductance, which is especially suitable for the power distribution and input and output signals that require strict control. The low impedance plane layer can greatly reduce the dead voltage transients of the power bus and greatly improve the EMI performance. This controlled signal line not only helps to reduce EMI, but also plays an important role in ensuring the integrity of import and export signals.